Integration of Chemical Mechanical Polishing as Pre Metal Planarization in a Sub Micron CMOS Process

The influence of incorporating Chemical Mechanical Polishing for pre metal planarization in a sub micron CMOS process on several electrical and structural parameters was studied. It was found that the sheet resistance is increased by a small amount. Another effect was a downward shift of the threshold voltage of the Metal-1 parasitic devices. This effect was not related to CMP, but to the removal of a 900 °C flow step from the processing. Although the shift is significant it is stable in time, and the threshold voltage is still well above the supply voltage. The conclusion was drawn that the introduction of CMP in a sub micron process does not involve insuparable problems.