DocumentCode :
1917639
Title :
Dielectric Layer Planarization using Chemical-Mechanical-Polishing
Author :
Bae, Y.T ; Kim, H.K. ; Lim, S.K. ; Choi, K.H.
Author_Institution :
Micro Process Development Team, R & D Center, Samsung Semiconductor, Wonmi-Ku, Buchon, Kyunggi-Do, Korea.
fYear :
1994
fDate :
11-15 Sept. 1994
Firstpage :
129
Lastpage :
132
Abstract :
Application of Chemical-mechanical-polishing of the dielectric layer in multilevel metallization is introduced. To acheive globally planarized dielectric surfaces in severe topologies, some structures using mask and stop layer or double deposited dielectric layers for selective polishing are proposed. The characteristics of this polishing process were studied on wafer with real device topology. Experimental results were founded by measuring electrical characteristics and electromigration of metal lines and monitoring the cross-sectional view of planarized dielectric layer in the wafer.
Keywords :
Chemical processes; Density measurement; Dielectric devices; Dielectric measurements; Electric variables; Electric variables measurement; Metallization; Planarization; Research and development; Topology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid State Device Research Conference, 1994. ESSDERC '94. 24th European
Conference_Location :
Edinburgh, Scotland
Print_ISBN :
0863321579
Type :
conf
Filename :
5435685
Link To Document :
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