Title :
A Controllable low-power dual-port embedded SRAM for DSP processor
Author :
Yang, Hao-I ; Chang, Ming-Hung ; Lin, Tay-Jyi ; Ou, Shih-Hao ; Deng, Siang-Sen ; Liu, Chih-Wei ; Hwang, Wei
Author_Institution :
Dept. of Electron. Eng. & Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu
Abstract :
In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A co-design of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable pre-charged bit-line, low voltage bit-line, and controllable data-retention power gating. Because the low-power control signals are generated by the DSP engine, the operating condition of the memory module can be arbitrarily adjusted by using software programming. The integration of low-power dual-port 8KB SRAM and the multi-threaded DSP engine is implemented in TSMC 130 nm CMOS technology. By using these techniques, the overall access power reduction of the DSP core is around 15.30%-16.84%.
Keywords :
CMOS integrated circuits; SRAM chips; digital signal processing chips; electronic engineering computing; integrated circuit design; low-power electronics; multi-threading; CMOS technology; circuit design; controllable data-retention power gating; controllable low-power dual-port embedded SRAM; controllable precharged bit-line; low voltage bit-line; low-power control signal; memory module; multithreaded DSP processor; size 130 nm; software programming; CMOS technology; Circuits; Digital signal processing; Digital signal processing chips; Energy consumption; Engines; Leakage current; Low voltage; Random access memory; Voltage control;
Conference_Titel :
Memory Technology, Design and Testing, 2007. MTDT 2007. IEEE International Workshop on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-1656-1
Electronic_ISBN :
1087-4852
DOI :
10.1109/MTDT.2007.4547610
