Title :
Optimization of Junction-Isolated Vertical npn and pnp BJTs in a Modular BiCMOS Smart-Power Process
Author :
von Arx, C. ; Feudel, T. ; Ryter, R. ; Strecker, N. ; Zingg, R.P. ; Fichtner, W.
Author_Institution :
Integrated Systems Laboratory, Swiss Fed. Inst. of Technology, CH-8092 Zÿrich. Tel: +41 1 632 5335 Fax: +41 1 252 0994 e-mail: vonarx@iis.ee.ethz.ch
Abstract :
Vertical bipolar transistors are added to CMOS processes in order to obtain superior analog and drive capabilities. If these transistors can be isolated, special applications like low-voltage designs for battery-operated circuits or amplifier designs for sensors become possible. We report on a modular 40 V BiCMOS process where junction-isolated vertical npn and pnp transistors have been added for smart-power purposes.
Keywords :
BiCMOS integrated circuits; Bipolar transistor circuits; Bipolar transistors; CMOS process; CMOS technology; Design optimization; Implants; Isolation technology; Plugs; Production systems;
Conference_Titel :
Solid State Device Research Conference, 1994. ESSDERC '94. 24th European
Conference_Location :
Edinburgh, Scotland
