DocumentCode
1918301
Title
RAMSES-D: DRAM fault simulator supporting weighted coupling fault
Author
Hsing, Yu-Tsao ; Wu, Song-Guang ; Wu, Cheng-Wen
Author_Institution
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu
fYear
2007
fDate
3-5 Dec. 2007
Firstpage
33
Lastpage
38
Abstract
Memory fault simulator is an important tool for memory test sequence optimization. Traditionally, we use fault count to calculate fault coverage. However, it cannot represent accurately the real coupling fault distribution. In this paper, we adopt the concept of weighted coupling fault targeting DRAM. We propose a weighted fault coverage function with assigning weight parameters to coupling faults. With the weighted function, we can use physical information to calculate coupling fault coverage. Experimental result shows that the weight of intra-word coupling fault can be 10% to 14%; while the original fault count method cannot distinguish the degree of importance between different memory configurations.
Keywords
DRAM chips; integrated circuit testing; DRAM fault simulator; RAMSES-D; intra-word coupling fault; memory fault simulator; memory test sequence optimization; real coupling fault distribution; weighted coupling fault targeting; Algorithm design and analysis; Automata; Circuit faults; Circuit simulation; Computational modeling; Electronics industry; Random access memory; Semiconductor device manufacture; Semiconductor device noise; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Technology, Design and Testing, 2007. MTDT 2007. IEEE International Workshop on
Conference_Location
Taipei
ISSN
1087-4852
Print_ISBN
978-1-4244-1656-1
Electronic_ISBN
1087-4852
Type
conf
DOI
10.1109/MTDT.2007.4547612
Filename
4547612
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