Title :
Complete re-estimation of the gate leakage current limit for sub-0.12um technologies (EOT= 1.8-2.8nm)
Author :
Bidaud, M. ; Arnaud, F. ; Autran, J.L. ; Barla, K.
Author_Institution :
STMicroelectronics, Crolles, France
fDate :
11-13 September 2000
Keywords :
CMOS technology; Current density; Current measurement; Density measurement; Inverters; Leakage current; MOS devices; MOSFETs; Threshold voltage; Tunneling;
Conference_Titel :
Solid-State Device Research Conference, 2000. Proceeding of the 30th European
Print_ISBN :
2-86332-248-6
DOI :
10.1109/ESSDERC.2000.194775
