Improved Hot-Carrier Reliability in a 0.5-μm TLM CMOS Process by Back-End Process Optimization

The hot-carrier (HC) reliability of various interlayer (ILD) and intermetal (IMD) dielectric stacks has been studied on nMOSFET´s of a 0.5-μm TLM CMOS process. A phosphosilicate glass (PSG) layer in the ILD strongly suppresses the enhanced HC degradation associated with the spin-on glass (SOG) used for planarization in the IMD. The diffusion barrier properties of the PSG effectively reduce hot-electron induced interface trap generation that is causing the observed gm-degradation.