Design of standard cells used in low-power ASIC´s exploiting the multiple-supply-voltage scheme

Author

Jinn-Shyan Wang ; Shieh, Shang-Jyh ; Wang, Jinn-Shyan ; Yeh, C.-W.

Author_Institution

Dept. of Electr. Eng., Nat. Chung Cheng Univ., Chia-Yi, Taiwan

fYear

1998

fDate

13-16 Sep 1998

Firstpage

119

Lastpage

123

Abstract

ASIC design utilizing the multiple-supply-voltage (MSV) scheme has been shown to be efficient in reducing the power consumption. A new layout style of standard cells to be used in ASIC designs is proposed to effectively exploit the advantages afforded by the MSV scheme. Each standard cell is designed to use two power rails that are fed with different supply voltages. Then, the cells can be butted together arbitrarily no matter whether the cells are supplied from a high or low voltage, and the existing P&R tool can place and route the circuit as usual. As compared to the design with only one supply voltage, the average saving of power consumption of the new design (using the new cells and adopting the MSV scheme) is over 30%, but the average area overhead is only about 8%. Meanwhile, the average interconnection length is only increased by about 7.5%

Keywords

VLSI; application specific integrated circuits; cellular arrays; integrated circuit layout; logic CAD; low-power electronics; network routing; average area overhead; average interconnection length; layout style; low-power ASICs; multiple-supply-voltage scheme; power consumption; routing; standard cells; Application specific integrated circuits; Degradation; Electronic design automation and methodology; Energy consumption; High speed integrated circuits; Integrated circuit interconnections; Low voltage; Rails; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International

Conference_Location

Rochester, NY

ISSN

1063-0988

Print_ISBN

0-7803-4980-6

Type

conf

DOI

10.1109/ASIC.1998.722815

Filename

722815