Title :
Abstract: Exploring Design Space of a 3D Stacked Vector Cache
Author :
Egawa, R. ; Endo, Yuta ; Takizawa, Hiroyuki ; Kobayashi, Hideo ; Tada, Jubee
Author_Institution :
Cyberscience Center, Sendai, Japan
Abstract :
Although 3D integration technologies with through silicon vias (TSVs) have expected to overcome the memory and power wall problems in the future microprocessor design, there is no promising EDA tools to design 3D integrated VLSIs. In addition, effects of 3D integration on microprocessor design have not been discussed well. Under this situation, this paper presents design approach of 3D stacked cache memories using existing EDA tools, and shows early performances evaluation of 3D stacked cache memories for vector processors.
Keywords :
cache storage; electronic design automation; microprocessor chips; three-dimensional integrated circuits; 3D integration technology; 3D stacked cache memory; 3D stacked vector cache; EDA tool; TSV; VLSI; design space; microprocessor design; through silicon vias; vector processor;
Conference_Titel :
High Performance Computing, Networking, Storage and Analysis (SCC), 2012 SC Companion:
Conference_Location :
Salt Lake City, UT
Print_ISBN :
978-1-4673-6218-4
DOI :
10.1109/SC.Companion.2012.270
