A low power transregional MOSFET model for complete power-delay analysis of CMOS gigascale integration (GSI)

A new compact transregional model for conventional surface channel inversion MOSFETs with continuous and smooth transitions at regional boundaries is introduced. The model, verified against MEDICI and HSPICE, describes all regions of operation, namely, subthreshold, linear, and saturation while including the effects of 1) carrier velocity saturation, 2) vertical and lateral high field mobility degradation, and 3) threshold voltage roll-off, all prominent characteristics of sub-micron devices. The key contribution of this model is the physical insight into the on/off current trade-off that ensues with voltage scaling and will be vital to future low power design. Utilizing the model for a complete power-delay analysis of CMOS circuit designs, analytical expressions are derived for: 1) propagation delay, 2) short circuit power (P_SC), and 3) static power (P_Static). Results from the total power (P_Total) consumption analysis indicate that P_SC and P_Static may constitute over 1/3 of P_Total in future low power/high performance CMOS GSI