SystemVerilog: The new standard

The SystemVerilog language is fast becoming the dominant language used in the design and verification of digital systems. From its roots in the Verilog language, the latest revision (IEEE 1800-2012) has grown into a multi-faceted language that solves problems previously requiring the combination of multiple languages. Each of the speakers in this session has been closely involved with, and contributed to, the development of SystemVerilog. They will share their views, from a user´s and from an implementer´s perspective on the current status and future direction of the language. The session will serve to introduce new and current users to the capabilities of the language, enticing them to adopt it for their next project. At the same time, research groups are encouraged to participate in developing SystemVerilog methodologies and tools, and suggest new directions for language improvement.