• DocumentCode
    1919495
  • Title

    The unique challenges of debugging design and verification code jointly in SystemVerilog

  • Author

    Rich, Dave

  • Author_Institution
    Design Verification Technologies Mentor Graphics, Inc. Fremont, CA
  • fYear
    2013
  • fDate
    24-26 Sept. 2013
  • Firstpage
    1
  • Lastpage
    7
  • Abstract
    The process for capturing a design and verification of that design has merged into a single language: SystemVerilog. The approach engineers take for debugging their design and verification code must also merge into a unified process. The currently available tools must mature to serve the debug needs of both design and verifications engineers. This paper identifies some of the different approaches and challenges created by the SystemVerilog language.
  • Keywords
    Debugging; Hardware; Hardware design languages; Instruction sets; Object oriented modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Specification & Design Languages (FDL), 2013 Forum on
  • Conference_Location
    Paris, France
  • ISSN
    1636-9874
  • Type

    conf

  • Filename
    6646661
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1919495