[Title page - 2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design]

fYear

2008

fDate

5-7 June 2008

Firstpage

1

Lastpage

1

Abstract

The following topics are dealt with: arithmetic circuits verification; semantics of system description languages; latency-insensitive hardware-software interfaces; on-the-fly equivalence checker based on Boolean equation systems; directed-logical testing for functional verification of microprocessors; deterministic multithreaded software synthesis from polychronous specifications; fault-tolerant real-time scheduler; LambdaRAM verification; wide-area distributed cache for high performance computing; on-chip communication design; and Bluespec SystemVerilog.

Keywords

Boolean functions; cache storage; circuit simulation; fault tolerance; hardware description languages; high level synthesis; integrated circuit testing; logic testing; microprocessor chips; program verification; random-access storage; system-on-chip; Bluespec SystemVerilog; LambdaRAM verification; arithmetic circuits verification; directed-logical testing; fault-tolerant real-time scheduler; high performance computing; latency-insensitive hardware-software interfaces; microprocessors functional verification; on-chip communication design; system description language; wide-area distributed cache;

fLanguage

English

Publisher

ieee

Conference_Titel

Formal Methods and Models for Co-Design, 2008. MEMOCODE 2008. 6th ACM/IEEE International Conference on

Conference_Location

Anaheim, CA

Print_ISBN

978-1-4244-2417-7

Type

conf

DOI

10.1109/MEMCOD.2008.4547673

Filename

4547673