• DocumentCode
    1919784
  • Title

    Area-Efficient ESD Protection Design without Additional Process Cost in 0.18 um Salicided CMOS Technology

  • Author

    Kawazoe, Hidechika ; Aoki, Eiji ; Fujii, Katsumasa

  • Author_Institution
    Sharp Corporation, Tenri, Nara, Japan
  • fYear
    2000
  • fDate
    11-13 September 2000
  • Firstpage
    516
  • Lastpage
    519
  • Keywords
    Breakdown voltage; CMOS process; CMOS technology; Circuits; Costs; Diodes; Electrostatic discharge; Process design; Protection; Thyristors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Device Research Conference, 2000. Proceeding of the 30th European
  • Print_ISBN
    2-86332-248-6
  • Type

    conf

  • DOI
    10.1109/ESSDERC.2000.194828
  • Filename
    1503758
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1919784