An architecture template based SoC transaction level modeling and simulation method

This paper presents a novel architecture template-based transaction-level modeling and simulation technique to support the fast exploration of on-chip architectures. System level design issues become critical with the increasingly complex integrated circuits and the time-to-market pressure continues relentlessly. Design reuse and early design decision for architecture such as function, communication, scheduling are a "must". Our technique is based on a transaction level architecture template exploration methodology in which a co-simulation of function, communication, scheduling is performed with the architecture described in an abstract manner. The template acts between system level task model and RTL cycle-accurate model, which can reduce the difficulty of mapping the system level task to RTL architecture directly. Architecture template-based transaction level simulation can tradeoff the speed and accuracy of simulation, Which can solve the problem that system level simulation is not accuracy enough and RTL simulation is not fast. A JPEG case study indicates that our exploration technique achieves simulation speedup and supports complete system simulation