Hardware Implementation of a Polyphase Filter Bank for MP3 Decoding

MP3 decoding is usually implemented in the software due to the complexity of its hardware solution. The aim of this work is the hardware implementation of the polyphase filter bank, the most computationally intensive operation in the MP3 decoder, in order to improve the decoder operation speed while saving power. The Altera´s Stratix EP1S10F780C6ES FPGA has been used as hardware support taking advantage of its architecture oriented to DSP applications. DSP Builder design tools have been used together with Matlab and Quartus II in order to simplify the design and simulation tasks. As a result, a synthesis polyphase filter bank, working in real time, was designed and tested.