Title :
The Coarse-Grained / Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units
Author :
Yu, Chi Wai ; Lamoureux, Julien ; Wilton, Steven JE ; Leong, Philip H W ; Luk, Wayne
Author_Institution :
Dept of Comput., Imperial Coll. London, London
Abstract :
This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and interconnect between embedded floating point units (FPUs) and the fine-grained logic fabric in FPGAs. The results show that (1) FPUs should be square, (2) FPUs should be positioned tightly near the center of the FPGA and (3) that the FPU pins should be arranged on four sides of the FPU.
Keywords :
embedded systems; field programmable gate arrays; floating point arithmetic; interconnections; logic design; network routing; FPGA; coarse-grained programmable logic; embedded floating-point arithmetic units; empirical study; fine-grained logic interface; interconnects; pin arrangement; routing architecture; Computer interfaces; Delay; Embedded computing; Fabrics; Field programmable gate arrays; Floating-point arithmetic; Integrated circuit interconnections; Programmable logic arrays; Programmable logic devices; Routing;
Conference_Titel :
Programmable Logic, 2008 4th Southern Conference on
Conference_Location :
San Carlos de Bariloche
Print_ISBN :
978-1-4244-1992-0
DOI :
10.1109/SPL.2008.4547733
