DocumentCode :
1920869
Title :
The Architecture of FDP FPGA Device
Author :
Lai, Jinmei ; Chen, Liguang ; Tu, Rui ; Wang, Jian ; Wang, Yuan ; Tong, Jiarong ; Wang, Yabin ; Zhang, Huowen
Author_Institution :
ASIC & Syst. State Key Lab., Fudan Univ., Shanghai
fYear :
2008
fDate :
26-28 March 2008
Firstpage :
69
Lastpage :
74
Abstract :
A novel FuDan programmable(FDP) FPGA device architecture was presented. The new 3-LUT based logic cell could increase logic density about 11% comparing with a traditional 4-input LUT. The uniquely hierarchy programmable routing fabrics and effective switch box could optimize the routing wire segments and make it possible for different length to connect directly and efficiently. The FDP FPGA device contains 1,600 programmable logic cells, 160 programmable IO Blocks and 16 K bits dual port block RAM IP Core. It was fabricated with SMIC 0.18 mum Logic 1P6M Salicide 1.8 V/3.3 V process, its die size is 6.1times6.6 mm2, with the package of QFP208.
Keywords :
field programmable gate arrays; programmable logic devices; FPGA; FuDan programmable device architecture; logic density; programmable logic cells; Fabrics; Field programmable gate arrays; Logic devices; Packaging; Programmable logic arrays; Programmable logic devices; Routing; Switches; Table lookup; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Programmable Logic, 2008 4th Southern Conference on
Conference_Location :
San Carlos de Bariloche
Print_ISBN :
978-1-4244-1992-0
Type :
conf
DOI :
10.1109/SPL.2008.4547734
Filename :
4547734
Link To Document :
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