Title :
Parallel-concurrent fault simulation
Author :
Saab, Daniel G. ; Hajj, Ibrahim N. ; Rahmeh, Joseph T.
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Abstract :
A fault simulation algorithm based on the partitioning of faults into groups, with the group size equal to the number of bits in the host computer word, is presented. The fault effects of a particular group are evaluated using parallel fault simulation techniques and propagated using concurrent fault simulation techniques. The speed of the algorithm depends on the circuit and on the fault-grouping criterion. Three static grouping criteria are examined and compared in terms of speed and memory requirements. A dynamic regrouping technique is developed and is shown to improve the performance of static grouping
Keywords :
digital simulation; fault location; logic testing; concurrent fault simulation techniques; dynamic regrouping technique; fault-grouping criterion; group size; grouping criteria; host computer word length; memory requirements; parallel concurrent fault simulation; parallel fault simulation techniques; partitioning of faults; speed requirements; word oriented operation; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer simulation; Concurrent computing; Ear; Laboratories; Logic circuits; Logic testing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63376
