Strategy for Sub 0.5μM Circuit Performance Prediction using Process and Device Simulation

This paper describes how simulation tools can be used in both optimising circuit performance and also in predicting parasitic capacitances associated with back end processing of silicon CMOS devices. A combination of the process simulator, TSUPREM4, the device simulator, MEDICI, and RAPHAEL (for capacitance simulations) is used [1]. Calibration issues are discussed, including Focused Ion Beam techniques for calibration of the capacitance simulations. Two examples are presented of how this strategy can be used to shorten process development time.