A VLSI Architecture Suitable for Mid-Level Image Processing

Author

Dessbesell, Gustavo F. ; Pacheco, Marcio A. ; Martins, Joao B dos S ; Molz, Rolf Fredi

Author_Institution

Dept. of Comput. & Electron. Fed., Univ. of Santa Maria, Santa Maria

fYear

2008

fDate

26-28 March 2008

Firstpage

87

Lastpage

92

Abstract

Despite the constant research in this field in the last 40 years, computer vision still remains as a very challenging task. Computer vision techniques used to be categorized into levels, according to the amount of cognition embodied and the output provided. Taking into account the 3-levels approach, the goal of this work is the development of a VLSI architecture suitable for mid-level processing tasks. A software evaluation has been followed by its hardware equivalent implementation. The resulting architecture takes 11,165 logic elements and proved to be around 2.5 times faster than its software counterpart.

Keywords

VLSI; computer vision; logic devices; VLSI architecture; computer vision; hardware equivalent implementation; logic elements; mid-level image processing; software evaluation; Character recognition; Cognition; Computer architecture; Computer vision; Image processing; Informatics; Labeling; Licenses; Pattern recognition; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Programmable Logic, 2008 4th Southern Conference on

Conference_Location

San Carlos de Bariloche

Print_ISBN

978-1-4244-1992-0

Type

conf

DOI

10.1109/SPL.2008.4547737

Filename

4547737