On the Reconfiguration Costs of Models for Partially Reconfigurable FPGAs

There exists several FPGA architectures that can be partially reconfigured at run-time. The advantage of partial run-time reconfiguration is that it allows to develop new algorithmic solutions for many applications. But a limiting factor for using frequent dynamic reconfiguration could be the reconfiguration overhead. In order to study the potential of frequent run-time reconfiguration it is interesting to investigate its costs and benefits from an abstract point of view and to develop new architectural concepts. In this paper, we provide a formal treatment of the reconfiguration costs and compare them for models of standard partially reconfigurable FPGAs and 2-level reconfigurable FPGAs.