Design and parametric analysis of 32nm OPAMP in CMOS and CNFET technologies for optimum performance

There is a need to explore emerging technologies based on carbon nanotube electronics as the CMOS technology is approaching its limits. This will help in quick commercialization of these promising technologies. This paper presents the design, performance analysis and comparison of a carbon nanotube FET (CNFET) based OPAMP with bulk CMOS for 32 nm technology node. The CNFET based OPAMP is optimized in terms of operating voltage, diameter and pitch of the carbon nanotubes along with the qualitative explanation of the obtained results using HSPICE. Furthermore, comparison of CNFET design with planar CMOS for same on chip area occupancy shows the superiority of the former in terms of 210% increase in Gain, settling time reduction by 45%, power reduction equal to 81% and extremely good noise performance for low power-low bandwidth applications depending upon the selection of the CNT diameter. Additionally, we propose an optimal design of the output stage of CNFET OPAMP by lowering the inter-nanotube distance (pitch) while keeping the width of the CNFET constant for better slewing performance. Furthermore, comparison between two technologies for same GBP performance has also been investigated.