TDES Implementation in a Reconfigurable Computing Enviroment

The objective of this project is to evaluate the performance of the algorithm TDES (Triple Data Encryption Standard), used for encryption on high speed Ethernet networks. The algorithm is implemented using a hardware acceleration methodology in a reconfigurable computing environment, through a hardware description language, referred as VHDL (very high speed integrated circuit hardware description language), based in a FPGA (field programmable gate array). The results of the evaluation will be compared with results of the test done over a traditional software solution implemented by OpenSSL. It will be possible with the comparison to determine which solution has the best performance.