Impact of parasitic elements on the spurious triggering pulse in synchronous buck converter

Limiting the spurious triggering pulse in the gate-source voltage of the lower MOSFET during the turn-on transition of the upper MOSFET is mandatory to prevent substantial switching loss and even shoot-through in the synchronous buck converter. This paper conducts an exhaustive investigation into the impact of the inherent parasitic elements on the spurious triggering pulse to facilitate a reliability-oriented design. An analytical model that considers the parasitic capacitances and inductances, reverse recovery characteristics of the body diode and the interaction between the upper and the lower MOSFETs is established to quantify this pulse. The spurious triggering pulse is found to stem from the induced increase in the gate voltage and the induced decrease in the source voltage. Variation in the magnitude of the spurious triggering pulse in regard to each parasitic element is identified accordingly. Experimental results of a practical synchronous buck converter affirm the theoretical analysis.