DocumentCode
1921397
Title
Hardware reduction based on M-CSS correlation improvements
Author
Funes, M.A. ; Donato, P.G. ; Hadad, M.N. ; Carrica, D.O.
Author_Institution
Lab. de Instrumentacion y Control, Univ. Nac. de Mar del Plata, Mar del Plata, Argentina
fYear
2009
fDate
1-2 Oct. 2009
Firstpage
17
Lastpage
21
Abstract
An improved architecture for simultaneous correlation of complementary sets of sequences is presented. Taking advantage of some redundancies of the correlation algorithm, the resources consumption is reduced, improving the performance of the correlator. The FPGA implementation performed with generic parameters is evaluated and compared with previous proposals.
Keywords
field programmable gate arrays; FPGA implementation; M-CSS correlation improvement; M-sequences complementary set; complementary set; correlation algorithm; field programmable gate arrays; hardware reduction; simultaneous correlation;
fLanguage
English
Publisher
ieee
Conference_Titel
Micro-Nanoelectronics, Technology and Applications, 2009. EAMTA 2009. Argentine School of
Conference_Location
San Carlos de Bariloche
Print_ISBN
978-1-4244-4835-7
Electronic_ISBN
978-9-8725-1029-9
Type
conf
Filename
5288905
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