Parallel Implementation of the Shortest Path Algorithm on FPGA

An implementation of a parallel version of the shortest path algorithm on a Virtex-II Pro FPGA device that computes the minimal distance in a graph in a more efficiently way than the classical algorithms is presented The paper shows how the hardware/software codesign process is applied in order to design the system using a PowerPC processor running Linux on a XUP Virtex-II Pro development board. The coprocessor´s hardware architecture is fully described as well as the software running in Linux that is in charge of transferring data between the host computer, the PPC and the application-specific coprocessor. The synthesis results are presented as well as a comparative study of speedups for the parallel and the sequential implementation of the algorithm, showing a good improvement from the presented version against a software version running in a PC.