Title :
Iddt Test Calibration using a Programmable Processing Array
Author :
Itskovich, Mikhail ; Plusquellic, James
Author_Institution :
Dept. of Comput. Sci. & Electr. Eng., Univ. of Maryland, Baltimore, MD
Abstract :
This paper proposes an area efficient signal processing architecture to perform IDDT test calibration through vector multiplication. The design follows the Field Programmable Array organization, and capitalizes on the unique behavior of binary encoded signals to implement compact multiply elements. Vectors with 8 bit values were multiplied at a rate of 300 kHz, independently of vector size.
Keywords :
calibration; field programmable gate arrays; integrated circuit testing; area efficient signal processing architecture; binary encoded signals; compact multiply elements; field programmable array organization; programmable processing array; quiescent current; transient current; vector multiplication; Arithmetic; Calibration; Circuit testing; Computer architecture; Electrical resistance measurement; Hardware; Impedance measurement; Probes; Semiconductor device measurement; Vectors;
Conference_Titel :
Programmable Logic, 2008 4th Southern Conference on
Conference_Location :
San Carlos de Bariloche
Print_ISBN :
978-1-4244-1992-0
DOI :
10.1109/SPL.2008.4547773
