DocumentCode
1922005
Title
40-Gbit/s D-type flip-flop and multiplexer circuits using InP HEMT
Author
Suzuki, Takumi ; Kano, H. ; Nakasha, Y. ; Takahashi, T. ; Imanishi, K. ; Ohnishi, H. ; Watanabe, Y.
Author_Institution
Fujitsu Labs. Ltd., Kanagawa, Japan
Volume
1
fYear
2001
fDate
20-24 May 2001
Firstpage
595
Abstract
We developed a novel design technique for a D-type flip-flop (D-FF) circuit that is based on a small-signal-equivalent circuit approach. This technique provides the best condition to operate the D-FF at a high frequency. Using this technique, we fabricated a master-slave D-FF using a 0.15-/spl mu/m InP HEMT technology. We achieved 40-Gbit/s operation with clear-eye-waveform patterns and reduced jitter.
Keywords
HEMT integrated circuits; III-V semiconductors; equivalent circuits; field effect digital integrated circuits; flip-flops; high-speed integrated circuits; indium compounds; integrated circuit design; optical communication equipment; 0.15 micron; 40 Gbit/s; D-type flip-flop circuit; InP; InP HEMT technology; design technique; master-slave flip-flop; multiplexer circuit; small-signal-equivalent circuit; Chromium; Circuits; Clocks; FETs; Flip-flops; HEMTs; Indium phosphide; Latches; Multiplexing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Symposium Digest, 2001 IEEE MTT-S International
Conference_Location
Phoenix, AZ, USA
ISSN
0149-645X
Print_ISBN
0-7803-6538-0
Type
conf
DOI
10.1109/MWSYM.2001.966964
Filename
966964
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