Guidelines for developing power stage layouts using normally-off SiC JFETs based on parasitic analysis

The increasing maturity and commercial availability of new fast-switching wide band-gap semiconductor devices, such as normally-off silicon carbide (SiC) junction field-effect transistors (JFETs) and SiC MOSFETs, lead to the possibility of developing highly dense power converters due to their capability of switching at high frequencies and high temperature operation. At high frequencies, the parasitic inductances of the printed circuit board (PCB) traces and these device intrinsic capacitances play larger roles in the converter performance. This paper focuses on the various degrees of influence that these parasitics have on the performance of a converter power stage, in particular when paralleling normally-off SiC JFETs. A dc-dc step-down converter is selected as a test bench for developing guidelines for aiding in the layout of converter power stages having fast-switching wide band-gap devices, in particular, normally-off SiC JFETs. These guidelines are then used to design the power stage of an interleaved indirect matrix converter (IMC). Experimental results attest to the benefits of the proposed guidelines.