• DocumentCode
    1923145
  • Title

    A Premetal BPSG Filled Deep Trench Isolation Technology for ECL-BiCMOS LSIs using CMP

  • Author

    Yoshida, Hiroshi ; Suzuki, Hisamitsu ; Kinoshita, Yasushi ; Imai, Kiyotaka ; Akimoto, Takeshi ; Tokashiki, Ken ; Madihian, Mohammad ; Yamazaki, Tohru

  • Author_Institution
    ULSI Device Development Laboratories, NEC Corporation, 1120, Shimokuzawa, Sagamihara, Kanagawa 229, Japan
  • fYear
    1995
  • fDate
    25-27 Sept. 1995
  • Firstpage
    367
  • Lastpage
    370
  • Abstract
    A newly developed BPSG filled deep trench isolation technology featuring trench formation at the end of the front end process is presented. A thick BPSG film is used as a trench filling material and interlayer dielectrics under-first level metal simultaneously. The process step counts in deep trench isolation process module is 70% smaller than that of a conventional process. The thick BPSG planarized interlayer dielectrics film can reduce the wiring capacitance and provides a fine pitch interconnection for scaled CMOS. Using this technology, a high performance/low cost ECL-BiCMOS LSI is achieved.
  • Keywords
    CMOS technology; Capacitance; Costs; Dielectric films; Dielectric materials; Filling; Inorganic materials; Isolation technology; Large scale integration; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Device Research Conference, 1995. ESSDERC '95. Proceedings of the 25th European
  • Conference_Location
    The Hague, The Netherlands
  • Print_ISBN
    286332182X
  • Type

    conf

  • Filename
    5435903