A novel GaAs MESFET for suppression of low temperature side gating

Author

Onodera, K. ; Kitahata, H.

Author_Institution

NEC Corp., Kawasaki, Japan

fYear

1989

fDate

22-25 Oct. 1989

Firstpage

215

Lastpage

218

Abstract

The key technology for GaAs ICs and LSIs at low-temperature operation (-30 degrees C) is the suppression of side gating of MESFETs. A novel FET structure for suppressing the side gating that has been obtained by analysis of the surface depletion layer of FETs is proposed. Two improvements has been introduced. One is a p/sup +/ isolation layer. This layer is surrounded by an n-type layer which is biased in minimum negative potential of the circuit. The other is a control gate on the thin SiO/sub 2/. These improvements suppress both surface and bulk side gate current.<>

Keywords

III-V semiconductors; Schottky gate field effect transistors; field effect integrated circuits; gallium arsenide; integrated circuit technology; large scale integration; semiconductor technology; -30 C; FET structure; GaAs; GaAs MESFET; SiO/sub 2/-GaAs; control gate; improvements; low-temperature operation; n-type layer; p/sup +/ isolation layer; semiconductors; side gating suppression; suppression of low temperature side gating; surface depletion layer; thin SiO/sub 2/; Boron; Circuits; FETs; Gallium arsenide; Large scale integration; MESFETs; National electric code; Semiconductor devices; Temperature control; Temperature dependence;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1989. Technical Digest 1989., 11th Annual

Conference_Location

San Diego, CA, USA

Type

conf

DOI

10.1109/GAAS.1989.69329

Filename

69329