Exploiting Speculative Thread-Level Parallelism Based on Transactional Memory

Thread level speculation (TLS) and Transactional memory (TM) are both promising way to enhance the performance of chip multiprocessor (CMP). The complexity of providing efficient memory accesses buffering mechanism in TLS can be supported by TM logically. This paper proposes a speculative multi-threading model based on transactional memory, including its special hardware, compiler and execution support. It´s a low-design-complexity approach to effective unified support for both TLS&TM. The experimental results show that our framework is competent to exploit the speculative thread-level parallelism with little parallel degree loss by the parallel & ordered transaction partition strategy.