Hardware based encryption for wireless networks

We present an encryption scheme that is based on Error Correcting Codes (ECC). This scheme has the potential for reducing hardware usage due to hardware reuse. In this scheme, instead of having separate unit for encryption and error correction, the two schemes are carried out as a single step thereby using only one unit. The scheme exploits the characteristics of the ECC, and channel for achieving secrecy. The pipelined architecture and the result of its FPGA implementation is presented. We also show that the scheme is secure against conventional attacks and has also passed randomization test.