Faster Placer for Island-Style FPGAs

In this paper, we propose a placement method for island-style FPGAs, based on fast yet very good initial placement followed by refinement using ultra-low temperature simulated annealing. The initial placement is the keystone of the method and the steps to obtain it are: top down coarse partitioning, allocation of partitions to regions on FPGA array, placement of logic blocks within each region and finally the IOs. The solutions thus obtained require 66% fewer moves i.e. about 3x speed-up during final iterative refinement by simulated annealing, whereas the quality of solution is on the average within 2% of optimal. The critical path length obtained after routing does not degrade for the set of 9 benchmark circuits