Title :
Finite field polynomial 16-bit multiplier for power constrained devices
Author :
Escobar, José Antonio Flores ; Rosales, Moisés Salinas ; López, José Velázquez
Author_Institution :
ESIME Culhuacan, Grad. Sch., IPN, Mexico City, Mexico
Abstract :
In this work a finite field polynomial multiplier is presented. The multiplier is based on two-step algorithm performing the multiplication with the add and shift algorithm. A FPGA was chosen to implement the multiplier design, resulting the multiplication performed on 256 AND gates.
Keywords :
field programmable gate arrays; logic gates; multiplying circuits; polynomials; public key cryptography; 256 AND gates; FPGA; finite field polynomial 16-bit multiplier design; power constrained devices; shift algorithm; two-step algorithm; Field programmable gate arrays; Finite element methods; Galois fields; Hardware; Logic gates; Polynomials; Vectors;
Conference_Titel :
Electrical Communications and Computers (CONIELECOMP), 2012 22nd International Conference on
Conference_Location :
Cholula, Puebla
Print_ISBN :
978-1-4577-1326-2
DOI :
10.1109/CONIELECOMP.2012.6189902
