Effective heuristics for timing driven constructive placement

We present a novel approach to path-based timing driven constructive placement based on simple yet effective heuristics. A novel circuit model is proposed. We have extended an existing pad placement technique for sequential circuits, the results for which are compared to the existing work by using the TimberWolf placement package for cell placement. In cell placement, demonstrated in this paper for combinational circuits, we have extended the method of defining the region for locating a cell (window) to minimise the interconnect delay. The window region is determined by the paths in the circuit, and the cells are chosen from the critical path. The placement approach and its experimental results are presented in detail. We also show the results of a study on the effectiveness of using subsets of the paths in the circuit for timing driven placement. We believe that our work is the first to comprehensively address the issue of pad placement, and to study the effectiveness of using subsets of the paths in the circuit in timing driven placement. These techniques are being adapted for use in VLSI placement in an industrial environment