DocumentCode :
1925079
Title :
Multi-level passive order reduction of interconnect networks
Author :
Khazaka, R. ; Nakhla, M.
Author_Institution :
Dept. of Electr. Eng., Carleton Univ., Ottawa, Ont., Canada
Volume :
2
fYear :
2001
fDate :
20-24 May 2001
Firstpage :
1155
Abstract :
This paper presents an efficient algorithm for transient simulation of multi-port interconnect networks in the presence of nonlinear terminations. Krylov-subspace order reduction techniques have been shown to provide a significant speed-up in the simulation of interconnect networks. These methods however are far from optimal, and the resulting macromodel contains many redundant poles. In this paper, a passive multi-level reduction technique is presented. The proposed method eliminates the redundant poles, thus resulting in significant CPU cost reduction.
Keywords :
circuit simulation; high-speed integrated circuits; integrated circuit interconnections; integrated circuit modelling; multiport networks; transient analysis; CPU cost reduction; Krylov-subspace order reduction techniques; macromodel; multi-level passive order reduction; multi-port interconnect networks; nonlinear terminations; redundant poles; transient simulation; Central Processing Unit; Circuit simulation; Costs; Frequency; Integrated circuit interconnections; Marine vehicles; Microelectronics; Packaging; Time domain analysis; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microwave Symposium Digest, 2001 IEEE MTT-S International
Conference_Location :
Phoenix, AZ, USA
ISSN :
0149-645X
Print_ISBN :
0-7803-6538-0
Type :
conf
DOI :
10.1109/MWSYM.2001.967096
Filename :
967096
Link To Document :
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