Error coding and loss cell recovery in asynchronous transfer mode

Author

Wu, W.W. ; Gray, C. ; Wu, M.U. ; Budinger, J. ; Kim, H.

Author_Institution

Consultare Technol. Group, USA

Volume

3

fYear

1996

fDate

18-21 Aug 1996

Firstpage

1223

Abstract

This paper addresses the research and development results of error coding methods in ATM applications. These results include new code implementation, parallel decoding processing, and novel code combination. Three codecs have been designed, developed, simulated and are preparing for hardware testing in field programmable gate array logics. For the single cell transmission, the cell header and the Information Field (IF) are protected independently. For multiple cell transmission, both the header and the IF are error protected simultaneously. The combined effect is loss cell recovery due to transmission error and/or interference. All three codecs will be implemented in a single VLSI chip of 22000 gates

Keywords

VLSI; asynchronous transfer mode; codecs; decoding; digital communication; error correction codes; field programmable gate arrays; forward error correction; ATM applications; FPGA logic; VLSI chip; asynchronous transfer mode; cell header; codecs; error coding; error protection; field programmable gate array; information field; interference; loss cell recovery; multiple cell transmission; parallel decoding processing; transmission error; Asynchronous transfer mode; Codecs; Decoding; Field programmable gate arrays; Hardware; Logic gates; Logic testing; Programmable logic arrays; Protection; Research and development;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996., IEEE 39th Midwest symposium on

Conference_Location

Ames, IA

Print_ISBN

0-7803-3636-4

Type

conf

DOI

10.1109/MWSCAS.1996.593124

Filename

593124