Title :
Double-RESURF 700 V n-channel LDMOS with best-in-class on-resistance
Author :
Hossain, Zia ; Imam, Mohamed ; Fulton, Joe ; Tanaka, Masami
Author_Institution :
ON Semicond., Phoenix, AZ, USA
Abstract :
This paper presents a double-RESURF lateral double-diffused MOS (LDMOS) transistor with a specific on-resistance of lower than 200 mΩ-cm2 while maintaining a breakdown voltage of over 750 V for use in the cost-effective high voltage integrated circuit (HVIC) chip. The proposed double-RESURF high voltage device is monolithically integrated with low voltage analog/logic control circuitry, and is 100% backwards-compatible to ON Semiconductor´s existing single-RESURF technology. Double-RESURF is a very complicated process to implement, and requires a well-designed device layout with complete charge balance among all the critical layers. This paper will demonstrate a painstaking optimization of key process and device geometrical parameters to maximize the benefits of the double-RESURF phenomenon in order to achieve the lowest on-resistance possible with the desired breakdown voltage.
Keywords :
MOS integrated circuits; MOSFET; circuit optimisation; integrated circuit layout; power integrated circuits; semiconductor device breakdown; 700 V; HVIC; breakdown voltage; charge balance; device geometrical parameters; device layout; double-RESURF n-channel LDMOS; high voltage integrated circuit chip; lateral double-diffused MOS transistor; on-resistance; optimization; Breakdown voltage; Conductivity; Design methodology; Implants; Integrated circuit technology; Low voltage; MOS devices; MOSFETs; Regulators; Voltage control;
Conference_Titel :
Power Semiconductor Devices and ICs, 2002. Proceedings of the 14th International Symposium on
Print_ISBN :
0-7803-7318-9
DOI :
10.1109/ISPSD.2002.1016190
