The Hardware Thread Interface Design and Adaptation on Dynamically Reconfigurable SoC

Nowadays, one of the challenges for creating a mixed hardware/software application on dynamically reconfigurable SoC is how to provide a unified programming model for hybrid hardware/software tasks and a portable interface adaptation for dynamically reconfigurable hardware tasks. In this paper, a POSIX-compliant hardware thread interface is proposed for data stream driven applications, serving for unified hardware/software multithread programming. At the same time, the stub/interface adaptation mechanism is also presented to support shared buffer based inter-thread communication/synchronization. At last, the experimental results on AES encryption/decryption hardware thread show that the interface design and adaptation could exploit programming transparency while effectively keep hardware efficiency.