Title :
Synthesis for logical initializability of synchronous finite state machines
Author :
Singh, Montelc ; Nowick, Steven M.
Author_Institution :
Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
Abstract :
We present a new method for the synthesis for logical initializability of synchronous state machines. The goal is to produce a gate-level implementation that is initializable when simulated by a 3-valued (0,1,X) simulator. We build on the approach of Cheng and Agrawal (1989,92) who constrain state assignment to translate functional initializability into logic initializability. We propose an alternative method which is guaranteed safe and not as conservative. In addition, we propose necessary and sufficient conditions on 2-level and multi-level logic synthesis to insure 3-valued simulation succeeds
Keywords :
finite state machines; logic design; state assignment; ternary logic; constrained state assignment; gate-level circuit; logical initializability; multi-level logic; synchronous finite state machine; synthesis; three-valued logic; two-level logic; Algorithm design and analysis; Automata; Circuit faults; Circuit simulation; Circuit synthesis; Computational modeling; Computer science; Encoding; Logic circuits; Sufficient conditions;
Conference_Titel :
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
0-8186-7755-4
DOI :
10.1109/ICVD.1997.567964
