Optimization of low voltage n-channel LDMOS devices to achieve required electrical and lifetime SOA

Two-dimensional modeling is used to help quantitatively predict the amount of degradation in LDMOS device parameters as a function of stress time. Assuming the same trap density in the oxide, two-dimensional (2D) modeling is used to determine device parameter degradation for different device designs. This modeling technique helps in optimizing the device and understanding the tradeoffs involved to achieve the required short-term (electrical, thermal) SOA (safe operating area) and long-term robustness (hot carrier degradation). A good agreement with measured data is obtained showing that simulation based 4-way optimization of LDMOS devices (optimization with respect to on-resistance (Rsp), breakdown voltage (BVdss), short-term SOA and long-term SOA) is possible.