Tolerating Memory Latency Using a Hardware-Based Active-Pushing Technique

The pre-sending technique, proposed from distributed shared memory systems, pushes data to cache instead of pulling,aiming at reducing the traffic of communication. On a purpose of effectively improving cache hit ratio, this paper proposes a hardware-based active-pushing technique, which directs data owners like lower-level of memory hierarchy to actively push the predicted data at the right moment to a upper level, which is closer to the CPU, therefore achieving the object of reducing memory stall time. Again, a further optimization aimed at the timeliness of active-pushing technique is introduced. The prefetching, pre-sending, active-pushing and optimized active-pushing technique are, respectively, simulated upon the microprocessor simulation platform of "Longtium" R2. Experimenting results show that both the active-pushing technique and the optimized one improve cache hit ratio significantly compared with the rest.