Title :
A compact cell design for a multiport register file
Author :
Li, Zhi ; Smith, E.D. ; Kwatra, S.C.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Toledo Univ., OH, USA
Abstract :
Intended for generated layout in embedded designs, an 11-transistor design gives one write port and three read ports. Single-sided writing and reading are done by overpowering weak feedback in the memory flip-flop´s and output data latches. Transistors are scaled and layout developed to form 64-word by 16-column blocks in 0.8 μm CMOS. The four-fold decoder and I/O requirements are partially integrated into the layout
Keywords :
CMOS memory circuits; SRAM chips; flip-flops; integrated circuit layout; 0.8 micron; CMOS IC; compact cell design; embedded designs; four-fold decoder; generated layout; memory flip-flop; multiport register file; output data latches; single-sided reading; single-sided writing; Bandwidth; Centralized control; Computer buffers; Decoding; Educational institutions; Latches; Layout; Performance gain; Registers; Writing;
Conference_Titel :
Circuits and Systems, 1996., IEEE 39th Midwest symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-7803-3636-4
DOI :
10.1109/MWSCAS.1996.593129
