DocumentCode :
1926460
Title :
Efficient decimal leading zero anticipator designs
Author :
Amin, Mohamed H. ; Eltantawy, Ahmed M. ; Khedr, Alhassan F. ; Fahmy, Hossam A H ; Naguib, Ahmed A.
fYear :
2011
fDate :
6-9 Nov. 2011
Firstpage :
139
Lastpage :
143
Abstract :
The leading zero anticipator (LZA) is a vital block in fast floating point addition and fused multiply-add (FMA) operations. So far, there is only one decimal LZA proposed in research literature. This paper introduces two decimal LZA designs, then a comparison between the three designs, the two proposed here and the previous proposed one, is performed.
Keywords :
floating point arithmetic; logic design; FMA; decimal LZA designs; decimal leading zero anticipator designs; fast floating point addition; fused multiply-add operations; Adders; Arrays; Delay; Digital arithmetic; Equations; Logic gates; Vectors; Decimal; FMA; LZA; LZD; floating point;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Systems and Computers (ASILOMAR), 2011 Conference Record of the Forty Fifth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
ISSN :
1058-6393
Print_ISBN :
978-1-4673-0321-7
Type :
conf
DOI :
10.1109/ACSSC.2011.6189972
Filename :
6189972
Link To Document :
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