DocumentCode :
1926510
Title :
On building general modular adders from standard binary arithmetic components
Author :
Jaberipur, G. ; Parhami, B. ; Nejati, S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Shahid Beheshti Univ., Tehran, Iran
fYear :
2011
fDate :
6-9 Nov. 2011
Firstpage :
154
Lastpage :
159
Abstract :
We introduce an excess-δ residue representation for residue number system (RNS) arithmetic, in which a flag bit selects one or the other subrange within the full range of n-bit values. We show that our new representation leads to simple modular arithmetic with arbitrary residues, while using standard arithmetic components such as carry-save and carry-propagate adders that have been extensively optimized for area, power, and a host of other composite figures of merit. Further advantages of a unified treatment, as opposed to a multiplicity of specialized schemes previously proposed in connection with particular classes of moduli such as 2n ± 1 and 2n - 2k ± 1, include simplified design process, verification, testing, and fault tolerance. Both gate-level analyses and VLSI synthesis results point to advantages in latency, area, and/or power compared with other proposed designs in the literature.
Keywords :
VLSI; adders; carry logic; logic gates; residue number systems; VLSI synthesis; arbitrary residue; binary arithmetic component; carry-propagate adder; carry-save adder; design process; excess-δ residue representation; fault tolerance; gate-level analysis; general modular adder; modular arithmetic; residue number system arithmetic; Adders; Delay; Dynamic range; Encoding; Fault tolerance; Fault tolerant systems; Logic gates;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Systems and Computers (ASILOMAR), 2011 Conference Record of the Forty Fifth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
ISSN :
1058-6393
Print_ISBN :
978-1-4673-0321-7
Type :
conf
DOI :
10.1109/ACSSC.2011.6189975
Filename :
6189975
Link To Document :
بازگشت