DocumentCode
1926932
Title
Impulse response of on-chip power supply networks under varying conditions
Author
Uematsu, Yutaka ; Osaka, Hideki ; Yagyu, Masayoshi ; Saito, Tatsuya
Author_Institution
Production Eng. Res. Lab., Hitachi, Ltd., Yokohama, Japan
fYear
2010
fDate
24-26 Aug. 2010
Firstpage
1
Lastpage
4
Abstract
This paper presents a method for modeling chip-package resonance using impulse response and for measuring waveforms under varying conditions. We evaluated chip-package resonance with the following variations in conditions: (i) with and without on-package capacitors; (ii) differing positions on the chip; (iii) differing points of observation outside the chip (probe points for the package capacitor and bypass capacitor on the printed circuit board); (iv) circuit activating ratios varying from 11% to 100%. The results suggest that a circuit equivalent to our test chip can be expressed as a single lumped circuit. The results also demonstrate the effectiveness of on-package capacitors in reducing extra anti-resonance.
Keywords
capacitors; integrated circuit design; integrated circuit noise; integrated circuit packaging; lumped parameter networks; power supply circuits; bypass capacitor; chip package resonance; extra antiresonance; impulse response; lumped circuit; on chip power supply network; on-package capacitor; printed circuit board; Capacitors; Impedance; Noise; Power supplies; RLC circuits; Semiconductor device measurement; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
CPMT Symposium Japan, 2010 IEEE
Conference_Location
Tokyo
Print_ISBN
978-1-4244-7593-3
Type
conf
DOI
10.1109/CPMTSYMPJ.2010.5679675
Filename
5679675
Link To Document