Optimized architecture for Floating Point computation Unit

As floating point operations are complex, hence its implementation in Field Programmable Gate Array (FPGAs) consumes large amount of resources. FPGAs becomes inefficient if Floating Point Units (FPUs) are unutilized, to overcome this issue, a novel architecture is proposed in this paper for optimizing the floating point computation units in hybrid FPGAs in terms of achieving a better reduction in both area and power. The proposed architecture involves an algorithmic (logarithmic) approach for computing floating point numerical operations. It performs all the four basic arithmetic operations using simple hardware like adders, look up tables and interpolation steps. This methodology is used to evaluate a variety of FPU architecture optimizations. The model is being evaluated by comparing with the existing architectures like embedded FPUs and other FPU units in the FPGAs in terms of area, power, speed and high throughput. The simulation results of our model in cadence encounter tool shows the proposed architecture scales nearly 28 percent area and consumes 36 percent less power than existing FPUs. And also our method scales very well with an increase in required accuracy compared to the existing techniques.