Primitive path delay fault identification

We present a novel and efficient method to identify all primitive single and multi path delay faults (PDFs) in multi-level combinational circuits. Our method is the first one to successfully target the primitive PDF identification problem for multi-level circuits-previous research results in this area have been limited either to the identification of primitive PDFs only for 2-level circuits, or to the identification of only a subset of the complete set of paths which need not be tested for delay faults. Our primitive PDF identification procedure is based on determining which paths or sets of paths determine the signal stabilization time at the circuit outputs. We demonstrate the feasibility of the approach for mid-sized benchmark circuits